Solid-state semiconductor lasers are important devices in applications such as high-speed printing systems and optoelectronic communication systems. Semiconductor lasers have become increasingly important in recent years. One of the most important applications of semiconductor lasers is in communication systems where fiber optic communication media are employed. With growth in electronic communication, communication speed has become more important in order to increase data bandwidth in electronic communication systems. Improved semiconductor lasers can play a vital roll in increasing data bandwidth in communication systems using fiber optic communication media such as local area networks (LANs), metropolitan area networks (MANs) and wide area networks (WANs). A preferred component for optical interconnection of electronic components and systems via optical fibers is, thus, a semiconductor laser.
One type of well-known semiconductor laser is a vertical cavity surface emitting laser (VCSEL). The current state of design and operation of VCSELs is well known. Recently, there has been an increased interest in VCSELs, although edge-emitting lasers are still currently used in some applications. A VCSEL is thus a light-emitting device well known in the art. A reason for the interest in VCSELs is that edge-emitting lasers can produce a beam with a large angular divergence, thereby making the efficient collection of the emitted beam more difficult. Furthermore, edge-emitting lasers cannot be tested until the wafer is cleaved into individual devices, the edges of which form the mirror facets of each device. On the other hand, not only does the beam of a VCSEL have a small angular divergence, a VCSEL emits light normal to the surface of the wafer. In addition, since VCSELs incorporate the mirrors monolithically in their design, they allow for on-wafer testing and the fabrication of one-dimensional or two-dimensional laser arrays.
In any semiconductor device, there is a complex interplay of performance requirements, layout and technology options, and fundamental physics that constrains the final design. This is definitely the case for VCSELs. A typical VCSEL configuration includes an active region between two mirrors, disposed one after another on the surface of the substrate wafer. An insulating region forces the current to flow through a small aperture, and the device lases perpendicular to the wafer surface (i.e., the “vertical” part of VCSEL). One type of VCSEL in particular, the proton VCSEL, wherein the insulating region is formed by a proton implantation, dominated the early commercial history of VCSELs. More recently, the oxide-guided VCSEL has become available. In this device, the insulating region is formed by partial oxidation of a thin, high aluminum-content layer within the structure of the mirror. This same oxidation process can be applied to other semiconductor structures, to produce both optoelectronic and purely electronic devices. Both proton and oxide VCSELs can be isolated in the wafer by proton bombardment.
There are a number of obvious design possibilities, such as the oxide thickness, vertical placement, and aperture diameter, as well as many others dealing with design of mirrors, active regions, and doping, all of which can affect the final performance. It is possible to establish a basic design and to produce a wide range of behaviors simply by adjusting the aperture diameters. In particular, decreasing the oxide aperture diameter generally decreases the threshold current, but this inevitably increases the device electrical resistance and thermal impedance, because the current must pass through a smaller constriction. As a result, there are inevitable size-related tradeoffs between performance and reliability. Similar decisions must be made about differential efficiency (primarily controlled by top and bottom mirror reflectivity), temperature performance (primarily controlled by alignment of Fabry-Perot cavity wavelength and gain peak wavelength), and speed (controlled by many factors). Invariably, however, the oxidation process induces a region surrounding the oxide, but not itself oxidized, to have a high resistance, due to the presence of defects originating during the oxidation.
One of the primary reasons proton-implanted VCSELs have been commercially successful is their outstanding reliability performance over the competing edge-emitting lasers. Because reliability is so critical for VCSEL users, there has been understandable concern about the reliability performance of the newer oxide VCSELs. As with many issues, this one does not have a simple answer. Oxide VCSEL manufacturers employ designs with significant differences in the epitaxial structure as well as thickness, sizing, and placement of the oxide aperture layer. Honeywell reliability testing, both on a variety of internal designs and on competitive products, has demonstrated a wide range of reliability results for different oxide VCSEL designs. These differences can affect reliability either by changing the magnitude of the effect of failure modes or by introducing new ones, such as mechanical stress due to differential thermal expansion of the oxide relative to the semiconductor material. Failure modes such as these can be insidious, as they may not be seen in high-temperature life tests. For these reasons, oxide VCSEL reliability must be assessed for each particular oxide design, and the reliability effects of design choices must be understood through extensive reliability testing.
Reliability performance for oxide VCSEL products is an important design and fabrication issue. By systematically testing numerous design options through statistical experimentation techniques, the reliability impact of such choices can be understood. Beyond life tests of the type described herein it is important to incorporate reliability process monitoring protocols into any VCSEL design and fabrication system. Such protocols can include, for example, qualifying each wafer for production use by assessing its parametric stability and long-term reliability through sample life testing, as well as quarterly long-term life testing of a sample from production stock.
Reliability results can affect one of the possible design decisions: aperture diameter. As mentioned earlier, each choice may be suitable for a particular application, so there is not necessarily one “best” option. Note that as utilized herein, the term “reliability” generally relates to the tendency of a device to wear out, or to the lifetime of the device itself. Short-term reliability effects are dominated by changes (i.e., an increase or decrease) in device characteristics and, thus, the need for device stabilization.
Life-testing methodologies have been described many times before. For example, Hawthorne, et al., “Reliability Study of 850 nm VCSELs for Data Communications,” 1996 IEEE International Reliability Physics Proceedings, 34, (1996), pp. 203-210, describes such a study and is incorporated herein by reference. In such a study, multiple wafers representing several epitaxial growth and chip fabrication lots can be employed—at least 3 lots for each chip type. Chips can be packaged in TO-style devices, subjected to standard production burn-in, and then placed on long-term life testing. Some of the groups may be subjected to air-to-air thermal shocks before starting life testing (this did not impact the results). The burn-in can be performed in dark, forced-air ovens at approximately ten different combinations of constant temperature and DC current. Periodically the parts can be removed from the oven and DC tested at room temperature. Failure can be defined as a 2 dB reduction in output power at a fixed current. While the VCSELs may degrade in a fairly graceful way during life testing (as opposed to sudden, catastrophic degradation), it is not necessary to attempt to estimate extrapolated failure times. Reported failure times are always reported for actual failures.
The primary failure mechanism in all cases (both for the oxide and the proton VCSEL) is most likely related to the presence or generation of dislocations. Edge dislocations that traverse the P-N junction move only as continuous loops by glide or climb along fixed crystallographic directions and form dark line defects (DLDs) by generating a high density of deep point defect traps along their path of motion. DLDs are dark because of the compensating and lifetime killing properties of the deep traps.
The laminar structure of a VCSEL can confine propagating dislocations entirely to the plane of the active region (quantum wells and barriers). As a result, the only orientation in which they would appear linear is parallel to the active plane, in which orientation there would be no illuminated region to contrast with the DLD. From the top, the only direction in which the degradation can practicably be observed, the VCSEL emission appears either to dim gradually, progressing inward from an edge, or to dim nearly uniformly over the entire area. Neither of these conditions is clearly evident at the 2-dB degradation utilized as an end-of-life definition, probably because only a tiny fraction of the outer edge of the active area is involved at that point. The DLDs typically become visible only at 90% or greater degradation.
Two items are required for the propagation of a DLD: a dislocation (or surface) traversing the junction and mechanical stress. As a practical matter, minority carriers would need to be present. Without minority carriers, the activation energy for DLD motion may be enormously increased. For example, this phenomena is indicated in Maeda, et al., “Enhanced Glide of Dislocations in GaAs Single Crystals by Electron Beam Irradiation,” Japanese Journal of Applied Physics, Vol. 20, No. 3 (1981), pp. L165-L168, which is incorporated herein by reference. If any one of these three items is missing there will not be DLD degradation. Some mechanical stress is inevitable in the VCSEL; even if not present as a residue of processing, stress will arise from thermal gradients induced by operation. Minority carriers are also inescapable consequences of operation.
Dislocations can come from a variety of sources. VCSEL material growth by MOCVD employs low dislocation density substrates, but the dislocation density is not zero and a small but finite possibility always exists that a substrate dislocation will traverse the P-N junction inside the diameter of the isolation implant. The central portion of the cavity is the most vulnerable. Substrate dislocations in the region under the oxide or gain guide implant will have a reduced effect due to the lateral debiasing. Even if a pre-existing dislocation or surface is not accessible in the region of flowing current, they can be generated in situ. Point defects can be generated near the oxidation layer, and the isolation proton implant produces a high density of point defects that define the perimeter of the P-N junction. Under forward bias, minority carriers that recombine non-radiatively on these point defects impart energy to the defects that allow them to move so as to lower the free energy in the crystal. Aggregation of point defects into a dislocation loop produces a nucleus for DLD propagation and subsequent degradation.
Degradation resulting from grown-in dislocations is generally fairly rapid. In the rare instances where it occurs, it can typically be detected and removed by a short operating burn-in. Generation of dislocations through aggregation of point defects is much slower. It is this mechanism that likely controls the wear-out life of VCSELs. While details of VCSEL degradation remain open issues, it involves a combination of the mechanisms above (and perhaps others) and appears to be fundamentally similar for proton and oxide VCSELs of all sizes.
Thus, defects may be generated in VCSEL devices which can diffuse and drift within a VCSEL structure over the operating life of the VCSEL, thereby resulting in unstable and poorly operating VCSEL devices, particularly in oxide VCSELs. In addition, the presence and amount of these defects, even if in a stable configuration, are difficult to control. Thus, the performance characteristics, which may depend on their presence and amount, will be more variable for devices containing them than for devices from which they have been removed. This removal may also afford different, otherwise unavailable, design opportunities; for example, the removal of the non-conducting zone from beneath an oxide layer may allow it to be placed closer to electrically sensitive regions of the VCSEL. It is this phenomenon that has prompted the present inventors to conclude that a need exists for a method and system for identifying and removing such defects. Removing such defects during the fabrication process makes it possible to optimize the VCSEL and/or other semiconductor devices in a stable and reproducible manner. The present inventors believe that the present invention disclosed herein solves this important need.